Implemented project structure
This commit is contained in:
Fabio Scotto di Santolo
@@ -0,0 +1,40 @@
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/* Target macros for riscv*-elf targets.
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Copyright (C) 1994-2023 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#define LINK_SPEC "\
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-melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
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%{mno-relax:--no-relax} \
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%{mbig-endian:-EB} \
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%{mlittle-endian:-EL} \
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%{shared}"
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/* Link against Newlib libraries, because the ELF backend assumes Newlib.
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Handle the circular dependence between libc and libgloss. */
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#undef LIB_SPEC
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#define LIB_SPEC \
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"--start-group -lc %{!specs=nosys.specs:-lgloss} --end-group " \
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"%{!nostartfiles:%{!nodefaultlibs:%{!nolibc:%{!nostdlib:%:riscv_multi_lib_check()}}}}"
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#undef STARTFILE_SPEC
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#define STARTFILE_SPEC "crt0%O%s crtbegin%O%s"
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#undef ENDFILE_SPEC
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#define ENDFILE_SPEC "crtend%O%s"
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#define RISCV_USE_CUSTOMISED_MULTI_LIB select_by_abi_arch_cmodel
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@@ -0,0 +1,227 @@
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/* Definition of RISC-V target for GNU compiler.
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Copyright (C) 2016-2023 Free Software Foundation, Inc.
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Contributed by Andrew Waterman (andrew@sifive.com).
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_RISCV_OPTS_H
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#define GCC_RISCV_OPTS_H
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enum riscv_abi_type {
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ABI_ILP32,
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ABI_ILP32E,
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ABI_ILP32F,
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ABI_ILP32D,
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ABI_LP64,
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ABI_LP64F,
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ABI_LP64D
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};
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extern enum riscv_abi_type riscv_abi;
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enum riscv_code_model {
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CM_MEDLOW,
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CM_MEDANY,
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CM_PIC
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};
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extern enum riscv_code_model riscv_cmodel;
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enum riscv_isa_spec_class {
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ISA_SPEC_CLASS_NONE,
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ISA_SPEC_CLASS_2P2,
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ISA_SPEC_CLASS_20190608,
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ISA_SPEC_CLASS_20191213
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};
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extern enum riscv_isa_spec_class riscv_isa_spec;
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/* Keep this list in sync with define_attr "tune" in riscv.md. */
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enum riscv_microarchitecture_type {
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generic,
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sifive_7
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};
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extern enum riscv_microarchitecture_type riscv_microarchitecture;
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enum riscv_align_data {
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riscv_align_data_type_xlen,
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riscv_align_data_type_natural
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};
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/* Where to get the canary for the stack protector. */
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enum stack_protector_guard {
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SSP_TLS, /* per-thread canary in TLS block */
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SSP_GLOBAL /* global canary */
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};
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enum riscv_multilib_select_kind {
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/* Select multilib by builtin way. */
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select_by_builtin,
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/* Select multilib by ABI, arch and code model. */
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select_by_abi_arch_cmodel,
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/* Select multilib by ABI only. */
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select_by_abi,
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};
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#define MASK_ZICSR (1 << 0)
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#define MASK_ZIFENCEI (1 << 1)
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#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
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#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
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#define MASK_ZAWRS (1 << 0)
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#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
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#define MASK_ZBA (1 << 0)
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#define MASK_ZBB (1 << 1)
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#define MASK_ZBC (1 << 2)
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#define MASK_ZBS (1 << 3)
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#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
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#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
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#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
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#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
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#define MASK_ZFINX (1 << 0)
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#define MASK_ZDINX (1 << 1)
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#define MASK_ZHINX (1 << 2)
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#define MASK_ZHINXMIN (1 << 3)
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#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
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#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
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#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
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#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
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#define MASK_ZBKB (1 << 0)
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#define MASK_ZBKC (1 << 1)
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#define MASK_ZBKX (1 << 2)
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#define MASK_ZKNE (1 << 3)
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#define MASK_ZKND (1 << 4)
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#define MASK_ZKNH (1 << 5)
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#define MASK_ZKR (1 << 6)
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#define MASK_ZKSED (1 << 7)
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#define MASK_ZKSH (1 << 8)
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#define MASK_ZKT (1 << 9)
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#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
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#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
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#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
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#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
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#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
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#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
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#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
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#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
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#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
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#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
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#define MASK_VECTOR_ELEN_32 (1 << 0)
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#define MASK_VECTOR_ELEN_64 (1 << 1)
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#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
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#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
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#define TARGET_VECTOR_ELEN_32 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
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#define TARGET_VECTOR_ELEN_64 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
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#define TARGET_VECTOR_ELEN_FP_32 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
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#define TARGET_VECTOR_ELEN_FP_64 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
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#define MASK_ZVL32B (1 << 0)
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#define MASK_ZVL64B (1 << 1)
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#define MASK_ZVL128B (1 << 2)
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#define MASK_ZVL256B (1 << 3)
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#define MASK_ZVL512B (1 << 4)
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#define MASK_ZVL1024B (1 << 5)
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#define MASK_ZVL2048B (1 << 6)
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#define MASK_ZVL4096B (1 << 7)
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#define MASK_ZVL8192B (1 << 8)
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#define MASK_ZVL16384B (1 << 9)
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#define MASK_ZVL32768B (1 << 10)
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#define MASK_ZVL65536B (1 << 11)
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#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
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#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
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#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
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#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
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#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
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#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
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#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
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#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
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#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
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#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
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#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
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#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
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#define MASK_ZICBOZ (1 << 0)
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#define MASK_ZICBOM (1 << 1)
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#define MASK_ZICBOP (1 << 2)
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#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
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#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
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#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
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#define MASK_ZFHMIN (1 << 0)
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#define MASK_ZFH (1 << 1)
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#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
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#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
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#define MASK_ZMMUL (1 << 0)
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#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
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#define MASK_SVINVAL (1 << 0)
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#define MASK_SVNAPOT (1 << 1)
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#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
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#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
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/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
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set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
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popcount to caclulate the minimal VLEN. */
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#define TARGET_MIN_VLEN \
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((riscv_zvl_flags == 0) \
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? 0 \
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: 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
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#define MASK_XTHEADBA (1 << 0)
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#define MASK_XTHEADBB (1 << 1)
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#define MASK_XTHEADBS (1 << 2)
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#define MASK_XTHEADCMO (1 << 3)
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#define MASK_XTHEADCONDMOV (1 << 4)
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#define MASK_XTHEADFMEMIDX (1 << 5)
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#define MASK_XTHEADFMV (1 << 6)
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#define MASK_XTHEADINT (1 << 7)
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#define MASK_XTHEADMAC (1 << 8)
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#define MASK_XTHEADMEMIDX (1 << 9)
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#define MASK_XTHEADMEMPAIR (1 << 10)
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#define MASK_XTHEADSYNC (1 << 11)
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#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
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#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
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#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
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#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
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#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
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#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
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#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
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#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
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#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
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#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
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#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
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#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
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#endif /* ! GCC_RISCV_OPTS_H */
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@@ -0,0 +1,245 @@
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/* Definition of RISC-V target for GNU compiler.
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Copyright (C) 2011-2023 Free Software Foundation, Inc.
|
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Contributed by Andrew Waterman (andrew@sifive.com).
|
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Based on MIPS target for GNU compiler.
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|
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This file is part of GCC.
|
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|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
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|
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#ifndef GCC_RISCV_PROTOS_H
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#define GCC_RISCV_PROTOS_H
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#include "memmodel.h"
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/* Symbol types we understand. The order of this list must match that of
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the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
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enum riscv_symbol_type {
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SYMBOL_ABSOLUTE,
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SYMBOL_PCREL,
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SYMBOL_GOT_DISP,
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SYMBOL_TLS,
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SYMBOL_TLS_LE,
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SYMBOL_TLS_IE,
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SYMBOL_TLS_GD
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};
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#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
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/* Routines implemented in riscv.cc. */
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extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
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extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
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extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
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extern int riscv_address_insns (rtx, machine_mode, bool);
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extern int riscv_const_insns (rtx);
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extern int riscv_split_const_insns (rtx);
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extern int riscv_load_store_insns (rtx, rtx_insn *);
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extern rtx riscv_emit_move (rtx, rtx);
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extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *, bool);
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extern bool riscv_split_symbol_type (enum riscv_symbol_type);
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extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
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extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode, bool);
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extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
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extern rtx riscv_subword (rtx, bool);
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extern bool riscv_split_64bit_move_p (rtx, rtx);
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extern void riscv_split_doubleword_move (rtx, rtx);
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extern const char *riscv_output_move (rtx, rtx);
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extern const char *riscv_output_return ();
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||||
#ifdef RTX_CODE
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extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
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extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
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extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
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#endif
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extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
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extern rtx riscv_legitimize_call_address (rtx);
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extern void riscv_set_return_address (rtx, rtx);
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extern bool riscv_expand_block_move (rtx, rtx, rtx);
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extern rtx riscv_return_addr (int, rtx);
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extern poly_int64 riscv_initial_elimination_offset (int, int);
|
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extern void riscv_expand_prologue (void);
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extern void riscv_expand_epilogue (int);
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||||
extern bool riscv_epilogue_uses (unsigned int);
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extern bool riscv_can_use_return_insn (void);
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extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
|
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extern bool riscv_expand_block_move (rtx, rtx, rtx);
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extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
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extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
|
||||
extern bool riscv_gpr_save_operation_p (rtx);
|
||||
extern void riscv_reinit (void);
|
||||
extern poly_uint64 riscv_regmode_natural_size (machine_mode);
|
||||
extern bool riscv_v_ext_vector_mode_p (machine_mode);
|
||||
extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
|
||||
extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
|
||||
extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
|
||||
extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel);
|
||||
|
||||
/* Routines implemented in riscv-c.cc. */
|
||||
void riscv_cpu_cpp_builtins (cpp_reader *);
|
||||
void riscv_register_pragmas (void);
|
||||
|
||||
/* Routines implemented in riscv-builtins.cc. */
|
||||
extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
|
||||
extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *);
|
||||
extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
|
||||
extern tree riscv_builtin_decl (unsigned int, bool);
|
||||
extern void riscv_init_builtins (void);
|
||||
|
||||
/* Routines implemented in riscv-common.cc. */
|
||||
extern std::string riscv_arch_str (bool version_p = true);
|
||||
extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
|
||||
|
||||
extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
|
||||
|
||||
rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
|
||||
rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
|
||||
|
||||
/* Information about one CPU we know about. */
|
||||
struct riscv_cpu_info {
|
||||
/* This CPU's canonical name. */
|
||||
const char *name;
|
||||
|
||||
/* Default arch for this CPU, could be NULL if no default arch. */
|
||||
const char *arch;
|
||||
|
||||
/* Which automaton to use for tuning. */
|
||||
const char *tune;
|
||||
};
|
||||
|
||||
extern const riscv_cpu_info *riscv_find_cpu (const char *);
|
||||
|
||||
/* Routines implemented in riscv-selftests.cc. */
|
||||
#if CHECKING_P
|
||||
namespace selftest {
|
||||
void riscv_run_selftests (void);
|
||||
} // namespace selftest
|
||||
#endif
|
||||
|
||||
namespace riscv_vector {
|
||||
#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
|
||||
#define RVV_VUNDEF(MODE) \
|
||||
gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \
|
||||
UNSPEC_VUNDEF)
|
||||
enum vlmul_type
|
||||
{
|
||||
LMUL_1 = 0,
|
||||
LMUL_2 = 1,
|
||||
LMUL_4 = 2,
|
||||
LMUL_8 = 3,
|
||||
LMUL_RESERVED = 4,
|
||||
LMUL_F8 = 5,
|
||||
LMUL_F4 = 6,
|
||||
LMUL_F2 = 7,
|
||||
NUM_LMUL = 8
|
||||
};
|
||||
|
||||
enum avl_type
|
||||
{
|
||||
NONVLMAX,
|
||||
VLMAX,
|
||||
};
|
||||
/* Routines implemented in riscv-vector-builtins.cc. */
|
||||
void init_builtins (void);
|
||||
const char *mangle_builtin_type (const_tree);
|
||||
#ifdef GCC_TARGET_H
|
||||
bool verify_type_context (location_t, type_context_kind, const_tree, bool);
|
||||
#endif
|
||||
void handle_pragma_vector (void);
|
||||
tree builtin_decl (unsigned, bool);
|
||||
gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
|
||||
rtx expand_builtin (unsigned int, tree, rtx);
|
||||
bool check_builtin_call (location_t, vec<location_t>, unsigned int,
|
||||
tree, unsigned int, tree *);
|
||||
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
|
||||
bool legitimize_move (rtx, rtx, machine_mode);
|
||||
void emit_vlmax_vsetvl (machine_mode, rtx);
|
||||
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
|
||||
void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
|
||||
void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
|
||||
void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
|
||||
enum vlmul_type get_vlmul (machine_mode);
|
||||
unsigned int get_ratio (machine_mode);
|
||||
int get_ta (rtx);
|
||||
int get_ma (rtx);
|
||||
int get_avl_type (rtx);
|
||||
unsigned int calculate_ratio (unsigned int, enum vlmul_type);
|
||||
enum tail_policy
|
||||
{
|
||||
TAIL_UNDISTURBED = 0,
|
||||
TAIL_AGNOSTIC = 1,
|
||||
TAIL_ANY = 2,
|
||||
};
|
||||
|
||||
enum mask_policy
|
||||
{
|
||||
MASK_UNDISTURBED = 0,
|
||||
MASK_AGNOSTIC = 1,
|
||||
MASK_ANY = 2,
|
||||
};
|
||||
enum tail_policy get_prefer_tail_policy ();
|
||||
enum mask_policy get_prefer_mask_policy ();
|
||||
rtx get_avl_type_rtx (enum avl_type);
|
||||
opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
|
||||
bool simm5_p (rtx);
|
||||
bool neg_simm5_p (rtx);
|
||||
#ifdef RTX_CODE
|
||||
bool has_vi_variant_p (rtx_code, rtx);
|
||||
#endif
|
||||
bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, machine_mode,
|
||||
bool, void (*)(rtx *, rtx));
|
||||
rtx gen_scalar_move_mask (machine_mode);
|
||||
|
||||
/* RVV vector register sizes.
|
||||
TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to
|
||||
support other values in the future. */
|
||||
enum vlen_enum
|
||||
{
|
||||
RVV_32 = 32,
|
||||
RVV_64 = 64,
|
||||
RVV_65536 = 65536
|
||||
};
|
||||
bool slide1_sew64_helper (int, machine_mode, machine_mode,
|
||||
machine_mode, rtx *);
|
||||
rtx gen_avl_for_scalar_move (rtx);
|
||||
}
|
||||
|
||||
/* We classify builtin types into two classes:
|
||||
1. General builtin class which is defined in riscv_builtins.
|
||||
2. Vector builtin class which is a special builtin architecture
|
||||
that implement intrinsic short into "pragma". */
|
||||
enum riscv_builtin_class
|
||||
{
|
||||
RISCV_BUILTIN_GENERAL,
|
||||
RISCV_BUILTIN_VECTOR
|
||||
};
|
||||
|
||||
const unsigned int RISCV_BUILTIN_SHIFT = 1;
|
||||
|
||||
/* Mask that selects the riscv_builtin_class part of a function code. */
|
||||
const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
|
||||
|
||||
/* Routines implemented in thead.cc. */
|
||||
extern bool th_mempair_operands_p (rtx[4], bool, machine_mode);
|
||||
extern void th_mempair_order_operands (rtx[4], bool, machine_mode);
|
||||
extern void th_mempair_prepare_save_restore_operands (rtx[4], bool,
|
||||
machine_mode,
|
||||
int, HOST_WIDE_INT,
|
||||
int, HOST_WIDE_INT);
|
||||
extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
|
||||
#ifdef RTX_CODE
|
||||
extern const char*
|
||||
th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
|
||||
#endif
|
||||
|
||||
#endif /* ! GCC_RISCV_PROTOS_H */
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user